Clock Configuration Modes
7
Clock Configuration Modes
As shown in this table, the clocking mode is set according to two sources:
• PCI_CFG[0]— An input signal. Also defined as “PCI_HOST_EN.” See Chapter 6, “External
Signals,” and Chapter 9, “PCI Bridge,” in the SoC reference manual.
• PCI_MODCK—Bit 27 in the Hard Reset Configuration Word. See Chapter 5, “Reset,” in the SoC
reference manual.
Table 16. SoC Clocking Modes
Pins
Clocking Mode
PCI_CFG[0]
1
0
0
1
1
1
2
PCI Clock Frequency Range (MHz)
Reference
PCI_MODCK
0
1
0
1
2
PCI host
50–66
25–50
PCI agent
50–66
25–50
PCI_HOST_EN
Determines PCI clock frequency range.
Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits
during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to
the selected clock operation mode as described in the following sections.
NOTE
Clock configurations change only after PORESET is asserted.
NOTE: Tval (Output Hold)
The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum
Tval = 1 ns when PCI_MODCK = 0. Therefore, designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
7.1
PCI Host Mode
These tables show configurations for PCI host mode. The frequency values listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does
not exceed the frequency rating of the user’s device. Note that in PCI host mode the input clock is the bus
clock.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
27
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
