DDR and DDR2 SDRAM
lists the PLL and DLL lock times.
Table 11. PLL and DLL Lock Times
Parameter/Condition
PLL lock times
DLL lock times
Min
—
7680
Max
100
122,880
Unit
μs
csb_clk cycles
Notes
—
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8347EA. Note that DDR SDRAM is GV
DD
(typ) = 2.5 V and DDR2 SDRAM is GV
DD
(typ) = 1.8 V.
The AC electrical specifications are the same for DDR and DRR2 SDRAM.
NOTE
The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware
Specifications.
See
for silicon revision level determination.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8347EA when GV
DD
(typ) = 1.8 V
.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV
DD
(typ) = 1.8 V
Parameter/Condition
I/O supply voltage
I/O reference voltage
I/O termination voltage
Input high voltage
Input low voltage
Output leakage current
Output high current (V
OUT
= 1.420 V)
Symbol
GV
DD
MV
REF
V
TT
V
IH
V
IL
I
OZ
I
OH
Min
1.71
0.49
×
GV
DD
MV
REF
– 0.04
MV
REF
+ 0.125
–0.3
–9.9
–13.4
Max
1.89
0.51
×
GV
DD
MV
REF
+ 0.04
GV
DD
+ 0.3
MV
REF
– 0.125
9.9
—
Unit
V
V
V
V
V
μA
mA
Notes
1
2
3
—
—
4
—
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
16
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
