DUART
shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
t
MCK
t
DDKHAS
,t
DDKHCS
t
DDKHAX
,t
DDKHCX
ADDR/CMD/MODT
Write A0
t
DDKHMP
t
DDKHMH
MDQS[n]
t
DDKHDS
t
DDKLDS
MDQ[x]
t
DDKHDX
D0
D1
t
DDKLDX
t
DDKHME
NOOP
Figure 7. DDR SDRAM Output Timing Diagram
provides the AC test load for the DDR bus.
Output
Z
0
= 50
Ω
R
L
= 50
Ω
GV
DD
/2
Figure 8. DDR AC Test Load
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8347EA.
7.1
DUART DC Electrical Characteristics
Table 21. DUART DC Electrical Characteristics
Parameter
Symbol
V
IH
V
IL
I
IN
Min
2
–0.3
—
Max
OV
DD
+ 0.3
0.8
±5
Unit
V
V
μA
provides the DC electrical characteristics for the DUART interface of the MPC8347EA.
High-level input voltage
Low-level input voltage
Input current (0.8 V
≤
V
IN
≤
2 V)
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
22
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
