I
2
C
12 I
2
C
This section describes the DC and AC electrical characteristics for the I
2
C interface of the MPC8347EA.
12.1
I
2
C DC Electrical Characteristics
Table 42. I
2
C DC Electrical Characteristics
provides the DC electrical characteristics for the I
2
C interface of the MPC8347EA.
At recommended operating conditions with OV
DD
of 3.3 V ± 10%.
Parameter
Input high voltage level
Input low voltage level
Low level output voltage
Output fall time from V
IH
(min) to V
IL
(max) with a bus
capacitance from 10 to 400 pF
Pulse width of spikes which must be suppressed by the
input filter
Input current each I/O pin (input voltage is between
0.1
×
OV
DD
and 0.9
×
OV
DD
(max)
Capacitance for each I/O pin
Symbol
V
IH
V
IL
V
OL
t
I2KLKV
t
I2KHKL
I
I
C
I
Min
0.7
×
OV
DD
–0.3
0
20 + 0.1
×
C
B
0
–10
—
Max
OV
DD
+ 0.3
0.3
×
OV
DD
0.2
×
OV
DD
250
50
10
10
Unit
V
V
V
ns
ns
μA
pF
Notes
—
—
1
2
3
4
—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C
B
= capacitance of one bus line in pF.
3. Refer to the
MPC8349EA Integrated Host Processor Family Reference Manual,
for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OV
DD
is switched off.
12.2
I
2
C AC Electrical Specifications
provides the AC timing parameters for the I
2
C interface of the MPC8347EA. Note that all values
refer to V
IH
(min) and V
IL
(max) levels (see
Table 43. I
2
C AC Electrical Specifications
Parameter
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
Data setup time
Data hold time:CBUS compatible masters
I
2
C bus devices
Symbol
1
f
I2C
t
I2CL
t
I2CH
t
I2SVKH
t
I2SXKL
t
I2DVKH
t
I2DXKL
Min
0
1.3
0.6
0.6
0.6
100
—
0
2
Max
400
—
—
—
—
—
—
0.9
3
Unit
kHz
μs
μs
μs
μs
ns
μs
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
46
Freescale Semiconductor