Package and Pin Listings
and
represent the AC timings from
Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
shows the SPI timings in slave mode (external clock).
SPICLK (Input)
t
NEIVKH
t
NEIXKH
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
t
NEKHOX
Note:
The clock edge is selectable on SPI.
Figure 38. SPI AC Timing in Slave Mode (External Clock) Diagram
shows the SPI timings in master mode (internal clock).
SPICLK (Output)
t
NIIVKH
t
NIIXKH
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
t
NIKHOX
Note:
The clock edge is selectable on SPI.
Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8347EA is available
in two packages—a tape ball grid array (TBGA) and a plastic ball grid array (PBGA). See
and
18.1
Package Parameters for the MPC8347EA TBGA
The package parameters are provided in the following list. The package type is 35 mm
×
35 mm, 672 tape
ball grid array (TBGA).
Package outline
35 mm
×
35 mm
Interconnects
672
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
54
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
