Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2.3.2
RMII Receive AC Timing Specifications
Table 29. RMII Receive AC Timing Specifications
shows the RMII receive AC timing specifications.
At recommended operating conditions with LV
DD
of 3.3 V ± 5%.
Parameter/Condition
Input low voltage at 3.3 LV
DD
Input high voltage at 3.3 LV
DD
REF_CLK clock period
REF_CLK duty cycle
REF_CLK peak-to-peak jitter
Rise time REF_CLK (20%–80%)
Fall time REF_CLK (80%–20%)
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
Symbol
V
IL
V
IH
t
RMR
t
RMRH
t
RMRJ
t
RMRR
t
RMRF
t
RMRDV
t
RMRDX
Min
—
2.0
15.0
35
—
1.0
1.0
4.0
2.0
Typical
—
—
20.0
50
—
—
—
—
—
Max
0.8
—
25.0
65
250
2.0
2.0
—
—
Unit
V
V
ns
%
ps
ns
ns
ns
ns
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
MRDVKH
symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
MRX
clock reference
(K) going to the high (H) state or setup time. Also, t
MRDXKL
symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the t
MRX
clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for eTSEC.
Output
Z
0
= 50
Ω
LVDD/2
R
L
= 50
Ω
Figure 13. eTSEC AC Test Load
MPC8377E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
29
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
