Overview
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— Four global high resolution timers/counters that can generate interrupts
— Supports additional internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
Two I
2
C controllers (one is contained within the CPM, the other is a stand-alone controller which
is not part of the CPM)
— Two-wire interface
— Multiple master support
— Master or slave I
2
C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the stand-alone I
2
C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I
2
C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (RXD, TXD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Two Three-speed (10/100/1000)Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers
— Support for Ethernet physical interfaces:
– 10/100/1000 Mbps IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
– 10 Mbps IEEE 802.3 MII
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
5
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
