I2C
12.2
I
2
C AC Electrical Specifications
Table 40. I
2
C AC Electrical Specifications
provides the AC timing parameters for the I
2
C interface of the MPC8541E.
All values refer to V
IH
(min) and V
IL
(max) levels (see
Parameter
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
Data setup time
Data hold time:
CBUS compatible masters
I
2
C bus devices
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Symbol
1
f
I2C
t
I2CL6
t
I2CH6
t
I2SVKH6
t
I2SXKL6
t
I2DVKH6
t
I2DXKL
Min
0
1.3
0.6
0.6
0.6
100
—
0
2
Max
400
—
—
—
—
—
—
0.9
3
300
300
—
—
—
—
Unit
kHz
μs
μs
μs
μs
ns
μs
t
I2CR
20 + 0.1 C
b 4
20 + 0.1 C
b 4
0.6
1.3
0.1
×
OV
DD
0.2
×
OV
DD
ns
ns
μs
μs
V
V
t
I2CF
t
I2PVKH
t
I2KHDX
V
NL
V
NH
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
I2DVKH
symbolizes I
2
C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
I2C
clock reference (K) going to the
high (H) state or setup time. Also, t
I2SXKL
symbolizes I
2
C timing (I2) for the time that the data with respect to the start
condition (S) went invalid (X) relative to the t
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
I2PVKH
symbolizes I
2
C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative
to the t
I2C
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2.
MPC8541E
provides a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum t
I2DVKH
has only to be met if the device does not stretch the LOW period (t
I2CL
) of the SCL signal.
4. C
B
= capacitance of one bus line in pF.
5. Guaranteed by design.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
50
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
