Clocking
15 Clocking
This section describes the PLL configuration of the MPC8541E. Note that the platform clock is identical
to the CCB clock.
15.1
Clock Ranges
provides the clocking specifications for the processor core and
provides the clocking
specifications for the memory bus.
Table 44. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
533 MHz
Min
e500 core
processor
frequency
400
Max
533
600 MHz
Min
400
Max
600
667 MHz
Min
400
Max
667
833 MHz
Min
400
Max
833
1000 MHz
Min
400
Max
1000
MHz 1, 2, 3
Unit Notes
Notes:
1.
Caution:
The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
and
for ratio settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3. 1000 MHz frequency supports only a 1.3 V core.
Table 45. Memory Bus Clocking Specifications
Maximum Processor Core
Frequency
Characteristic
533, 600, 667, 883, 1000 MHz
Min
Memory bus frequency
100
Max
166
MHz
1, 2, 3
Unit
Notes
Notes:
1.
Caution:
The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that
the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to
and
for ratio settings.
2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3. 1000 MHz frequency supports only a 1.3 V core.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
63
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
