Ethernet: Three-Speed, MII Management
Table 23. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter/Condition
RX_CLK clock period 10 Mbps
Symbol 1
Min
Typ
Max
Unit
2
tMRX
—
—
400
40
—
—
—
ns
ns
%
RX_CLK clock period 100 Mbps
tMRX
RX_CLK duty cycle
tMRXH MRX
tMRDVKH
tMRDXKH
/t
35
65
—
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
10.0
10.0
1.0
—
ns
ns
ns
—
—
2,3
tMRXR, tMRXF
—
4.0
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference
(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 10 shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXF
Valid Data
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRDVKH
tMRDXKH
Figure 10. MII Receive AC Timing Diagram
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
27
FREESCALE [ Freescale ]
