Package and Pin Listings
3.
4.
5.
6.
7.
Maximum solder ball diameter measured parallel to datum A.
Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
Capacitors may not be present on all devices.
Caution must be taken not to short capacitors or exposed metal capacitor pads on package top.
The socket lid must always be oriented to A1.
14.3
Pinout Listings
Table 43. MPC8555E Pinout Listing
Signal
Package Pin Number
PCI1 and PCI2 (one 64-bit or two 32-bit)
Pin Type
Power
Supply
Notes
Table 44
provides the pin-out listing for the MPC8555E, 783 FC-PBGA package.
PCI1_AD[63:32],
PCI2_AD[31:0]
AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14,
V15, W15, Y15, AA15, AB15, AC15, AD15, AG15,
AH15, V16, W16, AB16, AC16, AD16, AE16, AF16,
V17, W17, Y17, AA17, AB17, AE17, AF17, AF18
AH6, AD7, AE7, AH7, AB8, AC8, AF8, AG8, AD9,
AE9, AF9, AG9, AH9, W10, Y10, AA10, AE11, AF11,
AG11, AH11, V12, W12, Y12, AB12, AD12, AE12,
AG12, AH12, V13, Y13, AB13, AC13
AG13, AH13, V14, W14
AH8, AB10, AD11, AC12
AA11
Y14
AC10
AG10
AD10
V11
AH10
AA9
AE13
I/O
OV
DD
17
PCI1_AD[31:0]
I/O
OV
DD
17
PCI_C_BE64[7:4]
PCI2_C_BE[3:0]
PCI_C_BE64[3:0]
PCI1_C_BE[3:0]
PCI1_PAR
PCI1_PAR64/PCI2_PAR
PCI1_FRAME
PCI1_TRDY
PCI1_IRDY
PCI1_STOP
PCI1_DEVSEL
PCI1_IDSEL
PCI1_REQ64/PCI2_FRAME
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
OV
DD
17
17
2
2
2
2
2
5, 10
2
2
2, 4
PCI1_ACK64/PCI2_DEVSEL AD13
PCI1_PERR
PCI1_SERR
PCI1_REQ[0]
PCI1_REQ[1:4]
W11
Y11
AF5
AF3, AE4, AG4, AE5
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
57
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
