MPC8572EVTARLB 参数 Datasheet PDF下载

System Design Information

Figure 62

shows the PLL power supply filter circuits.

10

Ω

V

DD

2.2 µF

2.2 µF

Low ESL Surface Mount Capacitors

AV

DD

GND

Figure 62. PLL Power Supply Filter Circuit

NOTE

It is recommended to have the minimum number of vias in the AV

DD

trace

for board layout. For example, zero vias might be possible if the AV

DD

filter

is placed on the component side. One via might be possible if it is placed on

the opposite of the component side. Additionally, all traces for AV

DD

and

the filter components should be low impedance, 10 to 15 mils wide and

short. This includes traces going to GND and the supply rails they are

filtering.

The AV

DD

_SRDSn signal provides power for the analog portions of the SerDesn PLL. To ensure stability

of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in

following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the

AV

DD

_SRDSn ball to ensure it filters out as much noise as possible. The ground connection should be near

the AV

DD

_SRDSn ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF

capacitors, and finally the 1

Ω

resistor to the board supply plane. The capacitors are connected from

AV

DD

_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant

frequency. All traces should be kept short, wide and direct.

SV

DD_SRDSn

1.0

Ω

2.2 µF

1

2.2 µF

1

0.003 µF

AV

DD

_SRDSn

GND

1. An 0805 sized capacitor is recommended for system initial bring-up.

Figure 63. SerDes PLL Power Supply Filter

Note the following:

• AV

DD

_SRDSn should be a filtered version of SV

DD

_SRDSn.

• Signals on the SerDesn interface are fed from the XV

DD

_SRDSn power plane.

21.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8572E system, and the device

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each V

DD

, TV

DD

, BV

DD

, OV

DD

, GV

DD

, and LV

DD

pin

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

126

Freescale Semiconductor