Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 24. FIFO Mode Transmit AC Timing Specification (continued)
At recommended operating conditions with LV
DD
/TV
DD
of 2.5V ± 5%
Parameter/Condition
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Symbol
t
FITR
t
FITF
t
FITDV
t
FITDX
Min
—
—
2.0
0.5
Typ
—
—
—
—
Max
0.75
0.75
—
3.0
Unit
ns
ns
ns
ns
Notes:
1. The minimum cycle period (or maximum frequency) of the TX_CLK is dependent on the maximum platform frequency of the
speed bins the part belongs to as well as the FIFO mode under operation. Refer to
Section 4.5, “Platform to eTSEC FIFO
Restrictions,”
for more detailed description.
Table 25. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with LV
DD
/TV
DD
of 2.5V ± 5%
Parameter/Condition
RX_CLK clock period
1
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Symbol
t
FIR
t
FIRH
/t
FIR
t
FIRJ
t
FIRR
t
FIRF
t
FIRDV
t
FIRDX
Min
5.3
45
—
—
—
1.5
0.5
Typ
8.0
50
—
—
—
—
—
Max
100
55
250
0.75
0.75
—
—
Unit
ns
%
ps
ns
ns
ns
ns
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the
speed bins the part belongs to as well as the FIFO mode under operation. Refer to
Section 4.5, “Platform to eTSEC FIFO
Restrictions,”
for more detailed description.
Figure 8
show the FIFO timing diagrams.
t
FITF
t
FIT
GTX_CLK
t
FITH
TXD[7:0]
TX_EN
TX_ER
t
FITDV
t
FITDX
t
FITR
Figure 7. FIFO Transmit AC Timing Diagram
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
31
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
