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MPC8572EVTARLB 参数 Datasheet PDF下载

MPC8572EVTARLB图片预览
型号: MPC8572EVTARLB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC)  
Figure 12 shows the MII transmit AC timing diagram.  
t
t
MTXR  
MTX  
TX_CLK  
t
t
MTXH  
MTXF  
TXD[3:0]  
TX_EN  
TX_ER  
t
MTKHDX  
Figure 12. MII Transmit AC Timing Diagram  
8.2.3.2  
MII Receive AC Timing Specifications  
Table 29 provides the MII receive AC timing specifications.  
Table 29. MII Receive AC Timing Specifications  
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.  
1
Parameter/Condition  
Symbol  
Min  
Typ  
Max  
Unit  
2
RX_CLK clock period 10 Mbps  
RX_CLK clock period 100 Mbps  
RX_CLK duty cycle  
t
400  
40  
ns  
ns  
%
MRX  
t
MRX  
t
/t  
35  
65  
MRXH MRX  
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK  
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK  
RX_CLK clock rise (20%-80%)  
RX_CLK clock fall time (80%-20%)  
Notes:  
t
10.0  
10.0  
1.0  
1.0  
ns  
ns  
ns  
ns  
MRDVKH  
t
MRDXKH  
2
t
4.0  
4.0  
MRXR  
2
t
MRXF  
1. The symbols used for timing specifications herein follow the pattern of t  
(first two letters of functional block)(signal)(state) (reference)(state)  
for inputs and t  
for outputs. For example, t  
symbolizes MII receive  
(first two letters of functional block)(reference)(state)(signal)(state)  
MRDVKH  
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t  
clock reference (K)  
MRX  
going to the high (H) state or setup time. Also, t  
symbolizes MII receive timing (GR) with respect to the time data input  
MRDXKL  
signals (D) went invalid (X) relative to the t  
clock reference (K) going to the low (L) state or hold time. Note that, in general,  
MRX  
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For  
example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used  
MRX  
with the appropriate letter: R (rise) or F (fall).  
2. Guaranteed by design.  
Figure 13 provides the AC test load for eTSEC.  
Output  
Z = 50 Ω  
0
LV /2  
DD  
R = 50 Ω  
L
Figure 13. eTSEC AC Test Load  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
Freescale Semiconductor  
35