High-Speed Serial Interfaces (HSSI)
SDn_TX or
SDn_RX
A Volts
V
cm
= (A + B) / 2
SDn_TX or
SDn_RX
B Volts
Differential Swing, V
ID
or V
OD
= A – B
Differential Peak Voltage, V
DIFFp
= |A – B|
Differential Peak-Peak Voltage, V
DIFFpp
= 2*V
DIFFp
(not shown)
Figure 43. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, because
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V
OD
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, V
OD
is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (V
DIFFp
) is 500 mV. The peak-to-peak differential voltage (V
DIFFp-p
)
is 1000 mV p-p.
15.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for PCI Express and Serial RapidIO, or SD2_REF_CLK and SD2_REF_CLK for the
SGMII interface respectively.
The following sections describe the SerDes reference clock requirements and some application
information.
15.2.1
SerDes Reference Clock Receiver Characteristics
Figure 44
shows a receiver reference diagram of the SerDes reference clocks. Characteristics are as
follows:
• The supply voltage requirements for XV
DD_SRDS2
are specified in
Table 1
and
Table 2.
• SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in
Figure 44.
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has
on-chip 50-Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
73
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
