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MPC8572EVTARLB 参数 Datasheet PDF下载

MPC8572EVTARLB图片预览
型号: MPC8572EVTARLB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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PCI Express
Figure 55. Minimum Transmitter Timing and Voltage Output Compliance Specifications
16.4.3
Differential Receiver (RX) Input Specifications
Table 62
defines the specifications for the differential input at all receivers (RXs). The parameters are
specified at the component pins.
Table 62. Differential Receiver (RX) Input Specifications
Symbol
UI
Parameter
Unit Interval
Min
399.88
Nominal
400
Max
400.12
Units
ps
Comments
Each UI is 400 ps ± 300 ppm. UI does not
account for Spread Spectrum Clock
dictated variations. See Note 1.
V
RX-DIFFp-p
= 2*|V
RX-D+
- V
RX-D-
|
See Note 2.
The maximum interconnect media and
Transmitter jitter that can be tolerated by the
Receiver can be derived as T
RX-MAX-JITTER
= 1 - T
RX-EYE
= 0.6 UI.
See Notes 2 and 3.
V
RX-DIFFp-p
Differential Input
Peak-to-Peak
Voltage
Minimum
Receiver Eye
Width
0.175
1.200
V
T
RX-EYE
0.4
UI
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
86
Freescale Semiconductor