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MPC8572EVTARLB 参数 Datasheet PDF下载

MPC8572EVTARLB图片预览
型号: MPC8572EVTARLB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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Serial RapidIO
16.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2
inches of the package pins, into a test/measurement load shown in
Figure 57.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
Figure 57. Compliance Test/Measurement Load
17 Serial RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8572E
for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links.
Two transmitters (short run and long run) and a single receiver are specified for each of three baud rates,
1.25, 2.50, and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to
driving two connectors across a backplane. A single receiver specification is given that accepts signals
from both the short run and long run transmitter specifications.
The short run transmitter should be used mainly for chip-to-chip connections on either the same printed
circuit board or across a single connector. This covers the case where connections are made to a mezzanine
(daughter) card. The minimum swings of the short run specification reduce the overall power used by the
transceivers.
The long run transmitter specifications use larger voltage swings that are capable of driving signals across
backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications
allow a distance of at least 50 cm at all baud rates.
All unit intervals are specified with a tolerance of +/– 100 ppm. The worst case frequency difference
between any transmit and receive clock is 200 ppm.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
90
Freescale Semiconductor