Preliminary
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Block Diagram
SBW
REG
SBW
READ
ADD REG
WRITE0
ADD REG
WRITE1
ADD REG
SBW0
REG
Row Decode
SA0-SA18
DOC_MUX0
2:1 MUX
DOC_Array0
K
READ
Col Decode
Read/Wr Amp
LATCH
MATCH1
MATCH
SS
WRITE
WR_BUF1
ZZ
SW
LATCH0
DOC_MUX2
2:1 MUX
SW0
REG
SW1
REG
DOC_MUX1
2:1 MUX
DOC_
DOUT0
G
DQ0-DQ35
crlh3320.06
12/00
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Use is further subject to the provisions at the end of this document.
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WR_BUF0