Preliminary
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Power-Up and Power-Down Sequencing
The power supplies need to be powered up in the following manner: V
DD
, V
DDQ
, V
REF
, and Inputs. The
power-down sequencing must be the reverse. V
DDQ
can be allowed to exceed V
DD
by no more than 0.6V.
Clock Truth Table
K
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
X
ZZ
L
L
L
L
L
L
L
L
H
SS
L
L
L
L
L
L
L
H
X
SW
H
L
L
L
L
L
L
X
X
SBWa
X
L
H
H
H
L
H
X
X
SBWb
X
H
L
H
H
L
H
X
X
SBWc
X
H
H
L
H
L
H
X
X
SBWd
X
H
H
H
L
L
H
X
X
DQ (n)
X
X
X
X
X
X
X
X
High-Z
DQ (n+1)
D
OUT
0-35
D
IN
0-8
D
IN
9-17
D
IN
18-26
D
IN
27-35
D
IN
0-35
High-Z
High-Z
High-Z
MODE
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
Sleep Mode
Output Enable Truth Table
Operation
Read
Read
Sleep (ZZ = H)
Write (SW = L)
Deselect (SS = H)
G
L
H
X
X
X
DQ
D
OUT
0-35
High-Z
High-Z
High-Z
High-Z
crlh3320.06
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 27
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