ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)
Byte 0
Pin #
Name
Control Function Type
0
Functions
controlled by
Enables SMBus
RW
SW_EN
-
Bit 7
SMBus
Control
registers
RW
-
-
RESERVED
Bit 6
-
RESERVED
-
RW
Bit 5
-
RESERVED
RW
-
Bit 4
-
RESERVED
RW
-
Bit 3
-
RESERVED
RW
-
Bit 2
Selects PLL
PLL BW #adjust
-
RW
Low BW
Bit 1
Bandwidth
PLL bypassed
Bypasses PLL for
-
RW
PLL Enable
Bit 0
(fan out mode)
board test
SMBus Table: Output Enable Register
Byte 1
Pin #
Name
Control Function Type
-
RESERVED
RW
Bit 7
-
RESERVED
RW
Bit 6
-
RESERVED
RW
Bit 5
-
RESERVED
RW
Bit 4
-
RESERVED
RW
Bit 3
-
RESERVED
RW
Bit 2
-
RESERVED
RW
Bit 1
RESERVED
-
RW
Bit 0
SMBus Table: Function Select Register
Byte 2
Pin #
Name
Control Function Type
RESERVED
RW
Bit 7
RESERVED
RW
Bit 6
-
RW
RESERVED
Bit 5
-
RESERVED
RW
Bit 4
-
RESERVED
RW
Bit 3
-
RESERVED
RW
Bit 2
-
RESERVED
RW
Bit 1
-
RESERVED
RW
Bit 0
SMBus Table: Vendor & Revision ID Register
Byte 3
Pin #
Name
Control Function Type
-
RID3
R
Bit 7
-
RID2
R
Bit 6
REVISION ID
-
RID1
R
Bit 5
-
RID0
R
Bit 4
-
VID3
R
Bit 3
-
VID2
R
Bit 2
VENDOR ID
-
VID1
R
Bit 1
VID0
R
-
Bit 0
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
1
Functions
controlled by
device pins
PWD
1
X
X
X
X
X
High BW
PLL enabled
(ZDB mode)
1
1
0
-
-
-
-
-
-
-
-
1
PWD
X
X
X
X
X
X
X
X
0
-
-
-
-
-
-
-
-
1
PWD
X
X
X
X
X
X
X
X
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
1
0
0
0
1
852
REV K 04/01/10
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
