ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Electrical Characteristics - PLL Parameters
T
A
= Tambient; Supply Voltage V
DD
= 3.3 V +/-5%
Group
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Parameter
j
peak-hibw
j
peak-lobw
pll
HIBW
pll
LOBW
Description
(PLL_BW = 1)
(PLL_BW = 0)
(PLL_BW = 1)
(PLL_BW = 0)
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
Min
0
0
2
0.4
Typ
1
1
2.5
0.5
40
2.7
Max
2.5
2
3
1
108
3.1
Units
dB
dB
MHz
MHz
ps
ps rms
Notes
1,4
1,4
1,5
1,5
1,2,3
1,2,3
Jitter, Phase
t
jphasePLL
2.2
1.3
3.1
3
ps rms
ps rms
1,2,3
1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV K 04/01/10
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
