9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Pin Description
PIN # PIN NAME PIN TYPE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PLL_BW
SRC_IN
SRC_IN#
vOE0#
VDD
GND
DIF_0
DIF_0#
VDD
SMBDAT
SMBCLK
VDD
DIF_1#
DIF_1
GND
VDD
vOE1#
IN
IN
IN
IN
PWR
PWR
OUT
OUT
PWR
I/O
IN
PWR
OUT
OUT
PWR
PWR
IN
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Activ e low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Data pin of SMBUS c ircuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
Activ e low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
18
19
20
IREF
GNDA
VDDA
OUT
PWR
PWR
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT
®
Two Output Differential Buffer for PCIe Gen3
1667C—04/20/11
3
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
