ICS9UMS9633BI
Advance Information
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
SSOP Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
2
3
REF
GNDREF
VDDCORE_3.3
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
1 = All outputs are tri-stated for test
4
5
FSC_L
IN
IN
TEST_MODE
TEST_SEL
6
IN
IN
0 = All outputs behave normally.
Clock pin of SMBus circuitry, 5V tolerant.
7
8
9
SCLK
SDATA
VDDCORE_3.3
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V power for the PLL core
10 VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
11 DOT96C_LPR
12 DOT96T_LPR
OUT
OUT
13 GNDDOT
14 GNDLCD
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
15 LCD100C_LPR
16 LCD100T_LPR
OUT
OUT
17 VDDIO_1.5
18 VDDCORE_3.3
19 *CR#0
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
IN
Clock request for SRC0, 0 = enable, 1 = disable
20 GNDSRC
PWR Ground pin for the SRC outputs
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
21 SRCC0_LPR
22 SRCT0_LPR
OUT
OUT
23 *CR#1
IN
Clock request for SRC1, 0 = enable, 1 = disable
24 VDDCORE_3.3
PWR 3.3V power for the PLL core
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
1451—01/20/09
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
