ICS9UMS9633BI
Advance Information
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
MLF Pin Description
PIN #
1
PIN NAME
CPU_STOP#
TYPE
IN
DESCRIPTION
Stops all CPU clocks, except those set to be free running clocks
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
2
CLKPWRGD#/PD_3.3
IN
3
4
5
6
7
8
X2
X1
OUT Crystal output, Nominally 14.318MHz
IN Crystal input, Nominally 14.318MHz.
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
VDDREF_3.3
REF
GNDREF
VDDCORE_3.3
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
9
FSC_L
IN
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
10 TEST_MODE
IN
TEST_SEL: latched input to select TEST MODE
11 TEST_SEL
IN
IN
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
Clock pin of SMBus circuitry, 3.3V tolerant.
12 SCLK_3.3
13 SDATA_3.3
14 VDDCORE_3.3
15 VDDIO_1.5
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
16 DOT96C_LPR
17 DOT96T_LPR
OUT
OUT
18 GNDDOT
19 GNDLCD
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
20 LCD100C_LPR
21 LCD100T_LPR
OUT
OUT
22 VDDIO_1.5
23 VDDCORE_3.3
24 *CR#0
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
IN
Clock request for SRC0, 0 = enable, 1 = disable
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
1451—01/20/09
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
