IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
2.2.46 vcc—Power Supply (input)..............................................................................40
2.2.47 whb_n (IA186EM)—Write High Byte (synchronous output with
tristate)............................................................................................................40
2.2.48 wlb_n/wb_n—Write Low Byte (IA186EM) (synchronous output with
tristate)/Write Byte (IA188EM) (synchronous output with tristate) ..............40
2.2.49 wr_n—Write Strobe (synchronous output) ....................................................41
2.2.50 x1—Crystal Input (input) ...............................................................................41
2.2.51 x2—Crystal Input (input) ...............................................................................41
2.3 Pins Used by Emulators ..............................................................................................41
Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................42
Device Architecture..............................................................................................................43
4.1 Bus Interface and Control ...........................................................................................43
4.2 Clock and Power Management ...................................................................................45
4.3 System Clocks.............................................................................................................45
4.4 Power-Save Mode .......................................................................................................46
4.5 Initialization and Reset................................................................................................46
4.6 Reset Configuration Register ......................................................................................46
4.7 Chip Selects.................................................................................................................47
4.8 Chip-Select Timing .....................................................................................................47
4.9 Ready- and Wait-State Programming..........................................................................47
4.10 Chip Select Overlap ....................................................................................................47
4.11 Upper Memory Chip Select.........................................................................................48
4.12 Low Memory Chip Select ...........................................................................................49
4.13 Midrange Memory Chip Selects .................................................................................49
4.14 Peripheral Chip Selects ...............................................................................................49
4.15 Refresh Control ...........................................................................................................50
4.16 Interrupt Control..........................................................................................................50
4.16.1 Interrupt Types................................................................................................51
4.17 Timer Control..............................................................................................................52
4.18 Direct Memory Access (DMA)...................................................................................52
4.19 DMA Operation...........................................................................................................53
4.20 DMA Channel Control Registers ................................................................................53
4.21 DMA Priority ..............................................................................................................54
4.22 Asynchronous Serial Port............................................................................................54
4.23 Synchronous Serial Port..............................................................................................55
4.24 Programmable I/O (PIO).............................................................................................55
Peripheral Architecture.........................................................................................................57
5.1 Control and Registers..................................................................................................57
5.1.1 RELREG (0feh)..............................................................................................59
5.1.2 RESCON (0f6h)..............................................................................................59
5.1.3 PRL (0f4h)......................................................................................................59
5.1.4 PDCON (0f0h)................................................................................................60
5.1.5 EDRAM (0e4h) ..............................................................................................61
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