3 Volt Intel
®
Advanced+ Boot Block Flash Memory Stacked-CSP Family
program and erase operations, including verification, thereby unburdening the microprocessor or
microcontroller. The flash’s status register indicates the status of the WSM by signifying block
erase or word program completion and status.
Flash program and erase automation allows program and erase operations to be executed using an
industry-standard two-write command sequence to the CUI. Program operations are performed in
word increments. Erase operations erase all locations within a block simultaneously. Both program
and erase operations can be suspended by the system software in order to read from any other flash
block. In addition, data can be programmed to another flash block during an erase suspend.
The C3 Stacked-CSP memory device offers two low-power savings features: Automatic Power
Savings (APS) for flash memory and standby mode for flash and SRAM. The device automatically
enters APS mode following the completion of a read cycle from the flash memory. Standby mode
is initiated when the system deselects the device by driving F-CE# and S-CS1# or
S-CS2 inactive. Power savings features significantly reduce power consumption.
The flash memory can be reset by lowering F-RP# to GND. This provides CPU-memory reset
synchronization and additional protection against bus noise that may occur during system reset and
power-up/-down sequences.
1.3
72-
Package Ballout
Figure 1. 66-Ball Stacked Chip Scale Package
1
A
NC
B
2
3
A
20
A
16
4
A
11
A
8
5
A
15
A
10
A
21
6
A
14
A
9
7
A
13
8
9
10
11
12
NC
A
12
F-V
SS
F-V
CCQ
DQ
15
S-WE# DQ
14
DQ
7
DQ
13
DQ
6
DQ
4
DQ
5
C
F-WE# NC
D
S-V
SS
F-RP# A
22
E
F-WP# F-V
PP
A
19
F
S-LB# S-UB# S-OE#
G
A
18
H
NC
NC
A
5
A
4
A
0
F-CE# F-V
SS
F-OE# NC
NC
A
17
A
7
A
6
A
3
A
2
A
1
S-CS
1
#
DQ
9
DQ
8
DQ
0
DQ
1
DQ
11
DQ
10
DQ
2
DQ
3
DQ
12
S-CS
2
S-V
CC
F-V
CC
Top View, Balls Down
NOTES:
1. Flash upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash and SRAM
combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated). Ball
location A10 is “NC” on 16/2 devices only.
8
Datasheet
INTEL [ INTEL CORPORATION ]
