3 Volt Intel
®
Advanced+ Boot Block Flash Memory Stacked-CSP Family
2. To maintain compatibility with all JEDEC Variation B options for this ball location C6, this C6 land pad should
be connected directly to the land pad for ball G4 (A17).
1.4
Signal Definitions
Table 2. defines the signal definitions shown in the previous ballout.
Table 2.
Symbol
3 Volt Intel
®
Advanced+ Boot Block Stacked-CSP Ball Descriptions (Sheet 1 of 2)
Type
Name and Function
ADDRESS INPUTS
for memory addresses. Addresses are internally latched during a program or
erase cycle.
2-Mbit : A[16:0]
A[20:0]
INPUT
4-Mbit : A[18:0]
16-Mbit : A[19:0]
32-Mbit A[20:0]
DATA INPUTS/OUTPUTS:
Inputs array data for SRAM write operations and on the second F-CE#
and F-WE# cycle during a flash program command. Inputs commands to the flash’s Command
User Interface when F-CE# and F-WE# are asserted. Data is internally latched. Outputs array,
configuration and status register data. The data balls float to tri-state when the chip is de-selected
or the outputs are disabled.
FLASH CHIP ENABLE:
Activates the flash internal control logic, input buffers, decoders and
sense amplifiers. F-CE# is active low. F-CE# high de-selects the flash memory device and reduces
power consumption to standby levels.
SRAM CHIP SELECT1:
Activates the SRAM internal control logic, input buffers, decoders and
sense amplifiers. S-CS1# is active low. S-CS1# high de-selects the SRAM memory device and
reduces power consumption to standby levels.
SRAM CHIP SELECT2:
Activates the SRAM internal control logic, input buffers, decoders and
sense amplifiers. S-CS2 is active high. S-CS2 low de-selects the SRAM memory device and
reduces power consumption to standby levels.
FLASH OUTPUT ENABLE:
Enables flash’s outputs through the data buffers during a read
operation. F-OE# is active low.
SRAM OUTPUT ENABLE:
Enables SRAM’s outputs through the data buffers during a read
operation. S-OE# is active low.
FLASH WRITE ENABLE:
Controls writes to flash’s command register and memory array. F-WE#
is active low. Addresses and data are latched on the rising edge of the second F-WE# pulse.
SRAM WRITE ENABLE:
Controls writes to the SRAM memory array. S-WE# is active low.
SRAM UPPER BYTE ENABLE:
Enables the upper byte for SRAM (DQ
8
–DQ
15
).
S-UB# is active low.
SRAM LOWER BYTE ENABLE:
Enables the lower byte for SRAM (DQ
0
–DQ
7
).
S-LB# is active low.
FLASH RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to control reset/deep
power-down mode.
DQ[15:0]
INPUT /
OUTPUT
F-CE#
INPUT
S-CS1#
INPUT
S-CS2
INPUT
F-OE#
S-OE#
F-WE#
S-WE#
S-UB#
S-LB#
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
F-RP#
INPUT
When F-RP# is at logic low, the device is in reset/deep power-down mode,
which drives the
outputs to High-Z, resets the Write State Machine, and minimizes current levels (I
CCD
).
When F-RP# is at logic high, the device is in standard operation.
When F-RP# transitions from
logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.
Datasheet
9
INTEL [ INTEL CORPORATION ]
