82C54
If an initial count is written while GATE = 0, it will still be
loaded on the next CLK pulse. When GATE goes high, OUT
will go high N CLK pulses later; no CLK pulse is needed to
load the counter as this has already been done.
CW = 10
WR
CLK
GATE
OUT
N
N
N
N
0
4
0
3
0
2
0
1
0
0
FF
FF
FF
FE
LSB = 4
MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT
OUT will be initially high. OUT will go low on the CLK pulse
following a trigger to begin the one-shot pulse, and will remain
low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is
armed. A trigger results in loading the Counter and setting
OUT low on the next CLK pulse, thus starting the one-shot
pulse N CLK cycles in duration. The one-shot is retriggerable,
hence OUT will remain low for N CLK pulses after any trigger.
The one-shot pulse can be repeated without rewriting the
same count into the counter. GATE has no effect on OUT.
If a new count is written to the Counter during a one-shot
pulse, the current one-shot is not affected unless the
Counter is retriggerable. In that case, the Counter is loaded
with the new count and the one-shot pulse continues until
the new count expires.
CW = 12
WR
LSB = 3
CW = 10
WR
CLK
GATE
OUT
N
N
LSB = 3
N
N
0
3
0
2
0
2
0
2
0
1
0
0
FF
FF
CLK
CW = 10
WR
CLK
GATE
OUT
N
N
LSB = 3
LSB = 2
GATE
OUT
N
N
N
N
N
0
3
0
2
0
1
0
0
FF
FF
0
3
0
2
N
N
0
3
0
2
0
1
0
2
0
1
0
0
FF
FF
WR
CW = 12
LSB = 3
FIGURE 9. MODE 0
NOTES: The following conventions apply to all mode timing diagrams.
1. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS always low).
3. CW stands for “Control Word”; CW = 10 means a control word of
10, Hex is written to the counter.
4. LSB stands for Least significant “byte” of count.
5. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the counter is programmed to read/write
LSB only, the most significant byte cannot be read.
6. N stands for an undefined count.
7. Vertical lines show transitions between count values.
CLK
OUT
N
N
N
N
N
0
3
0
2
0
1
0
3
0
2
0
1
0
0
CLK
GATE
CW = 12
WR
LSB = 2
LSB = 4
GATE
OUT
N
N
N
N
N
0
2
0
1
0
0
FF
FF
FF
FE
0
4
0
3
FIGURE 10. MODE 1
12
INTERSIL [ INTERSIL CORPORATION ]
