ICL7660S
Typical Performance Curves
(Test Circuit Figure 12)
(Continued)
V+ = 5V
T
A
= 25
o
C
I = 10mA
C
1
= C
2
=
10µF
C
1
= C
2
=
100µF
400
OUTPUT RESISTANCE (Ω)
C
1
= C
2
=
1µF
300
200
100
0
100
1k
10k
100k
OSCILLATOR FREQUENCY (Hz)
FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY
NOTE:
7. These curves include in the supply current that current fed directly into the load R
L
from the V+ (See Figure 12). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally,
V
OUT
∼
2V
IN
, I
S
∼
2I
L
, so V
IN
x I
S
∼
V
OUT
x I
L
.
Detailed Description
The ICL7660S contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
2 external capacitors which may be inexpensive 10µF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 13,
which shows an idealized negative voltage converter.
Capacitor C
1
is charged to a voltage, V+, for the half cycle
when switches S
1
and S
3
are closed. (Note: Switches S
2
and S
4
are open during this half cycle.) During the second
half cycle of operation, switches S
2
and S
4
are closed, with
S
1
and S
3
open, thereby shifting capacitor C
1
to C
2
such
that the voltage on C
2
is exactly V+, assuming ideal switches
and no load on C
2
. The ICL7660S approaches this ideal
situation more closely than existing non-mechanical circuits.
V+
I
S
V+
1
2
C
1
+
10µF
-
3
4
ICL7660S
8
7
6
5
I
L
R
L
(+5V)
must always remain reverse biased with respect to their
sources, but not so much as to degrade their “ON”
resistances. In addition, at circuit start up, and under output
short circuit conditions (V
OUT
= V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
This problem is eliminated in the ICL7660S by a logic network
which senses the output voltage (V
OUT
) together with the
level translators, and switches the substrates of S
3
and S
4
to
the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660S is an integral
part of the anti-latchup circuitry, however its inherent voltage
drop can degrade operation at low voltages. Therefore, to
improve low voltage operation “LV” pin should be connected
to GND, disabling the regulator. For supply voltages greater
than 3.5V the LV terminal must be left open to insure latchup
proof operation, and prevent device damage.
-
V
OUT
C
2
10µF
Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficiency
if certain conditions are met:
1. The drive circuitry consumes minimal power.
-
+
NOTE: For large values of C
OSC
(>1000pF) the values of C
1
and C
2
should be increased to 100µF.
FIGURE 12. ICL7660S TEST CIRCUIT
2. The output switches have extremely low ON resistance
and virtually no offset.
3. The impedance of the pump and reservoir capacitors are
negligible at the pump frequency.
In the ICL7660S, the 4 switches of Figure 13 are MOS power
switches; S
1
is a P-Channel devices and S
2
, S
3
and S
4
are
N-Channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S
3
and S
4
3-40
INTERSIL [ INTERSIL CORPORATION ]
