ICL7660S
The ICL7660S approaches these conditions for negative
voltage conversion if large values of C
1
and C
2
are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS.
The energy lost is defined by:
E =
1
/
2
C
1
(V
12
- V
22
)
where V
1
and V
2
are the voltages on C
1
during the pump
and transfer cycles. If the impedances of C
1
and C
2
are
relatively high at the pump frequency (refer to Figure 13)
compared to the value of R
L
, there will be substantial
difference in the voltages V
1
and V
2
. Therefore it is not only
desirable to make C
2
as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C
1
in order to achieve maximum efficiency of
operation.
8
V
IN
C
1
S
1
2
S
2
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages. Figure
14 shows typical connections to provide a negative supply
where a positive supply of +1.5V to +12V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltage below 3.5V.
V+
1
10µF
+
2
3
4
ICL7660S
8
7
6
5
R
O
V
OUT
-
-
-
V
OUT
=
-
V+
V+
+
10µF +
3
3
14A.
14B.
C
2
S
3
4
S
4
5
V
OUT
=
-
V
IN
FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS
OUTPUT EQUIVALENT
7
FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER
Do’s and Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.
3. Do not short circuit the output to V
+
supply for supply
voltages above 5.5V for extended periods, however, tran-
sient conditions including start-up are okay.
4. When using polarized capacitors, the + terminal of C
1
must be connected to pin 2 of the ICL7660S and the +
terminal of C
2
must be connected to GND.
5. If the voltage supply driving the ICL7660S has a large
source impedance (25Ω - 30Ω), then a 2.2µF capacitor
from pin 8 to ground may be required to limit rate of rise
of input voltage to less than 2V/µs.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions.
A 1N914 or similar diode placed in parallel with C
2
will
prevent the device from latching up under these condi-
tions. (Anode pin 5, Cathode pin 3).
The output characteristics of the circuit in Figure 14 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 14B. The voltage source has
a value of -(V+). The output impedance (R
O
) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 13), the switching frequency, the value of C
1
and C
2
,
and the ESR (equivalent series resistance) of C
1
and C
2
. A
good first order approximation for R
O
is:
R
O
≅
2(R
SW1
+ R
SW3
+ ESR
C1
) + 2(R
SW2
+ R
SW
4 + ESR
C1
)
+
1
f
PUMP
x
C
1
(f
PUMP
=
+ ESR
C2
f
OSC
2
, R
SWX
= MOSFET switch resistance)
Combining the four R
SWX
terms as R
SW
, we see that:
1
R
O
≅
2 x R
SW
+
f
PUMP
x
C
1
+ 4 x ESR
C1
+ ESR
C2
Ω
R
SW
, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
graphs), typically 23Ω at 25
o
C and 5V. Careful selection of C
1
and C
2
will reduce the remaining terms, minimizing the output
impedance. High value capacitors will reduce the 1/(f
PUMP
x
C
1
) component, and low ESR capacitors will lower the ESR
term. Increasing the oscillator frequency will reduce the
1/(f
PUMP
x C
1
) term, but may have the side effect of a net
increase in output impedance when C
1
> 10µF and is not long
3-41
INTERSIL [ INTERSIL CORPORATION ]
