PX3511A, PX3511B
Electrical Specifications
PARAMETER
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT
Upper Drive Source Current (Note 4)
Upper Drive Source Impedance
Upper Drive Sink Current (Note 4)
Upper Drive Sink Impedance
Lower Drive Source Current (Note 4)
Lower Drive Source Impedance
Lower Drive Sink Current (Note 4)
Lower Drive Sink Impedance
NOTE:
4. Guaranteed by design. Not 100% tested in production.
I
U_SOURCE
V
PVCC
= 12V, 3nF Load
R
U_SOURCE
150mA Source Current
I
U_SINK
R
U_SINK
I
L_SOURCE
V
PVCC
= 12V, 3nF Load
150mA Sink Current
V
PVCC
= 12V, 3nF Load
-
1.4
-
0.9
-
0.85
-
0.60
1.25
2.0
2
1.65
2
1.3
3
0.94
-
3.0
-
3.0
-
2.2
-
1.35
A
Ω
A
Ω
A
Ω
A
Ω
t
TSSHD
t
RU
t
RL
t
FU
t
FL
t
PDHU
t
PDHL
t
PDLU
t
PDLL
t
PDTS
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
TEST CONDITIONS
VCC = 12V
MIN
-
-
-
-
-
-
-
-
-
-
-
TYP
1.96
245
26
18
18
12
10
10
10
10
10
MAX
-
-
-
-
-
-
-
-
-
-
-
UNITS
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L_SOURCE
150mA Source Current
I
L_SINK
R
L_SINK
V
PVCC
= 12V, 3nF Load
150mA Sink Current
Functional Pin Description
PACKAGE PIN #
SOIC
1
2
DFN
1
2
PIN
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
No Connection.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives in PX3511B; only the lower gate drive in PX3511A.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
-
3
3,8
4
N/C
PWM
4
5
6
7
8
9
5
6
7
9
10
11
GND
LGATE
VCC
PVCC
PHASE
PAD
5
FN6462.0
February 26, 2007
INTERSIL [ INTERSIL CORPORATION ]
