X9241A
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
100,000
100
UNIT
Data changes per bit per register
Years
Capacitance
SYMBOL
C
I/O(5)
C
IN(5)
PARAMETER
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
TEST CONDITION
V
I/O
= 0V
V
IN
= 0V
MAX
19
12
UNIT
pF
pF
Power-up Timing
SYMBOL
t
PUR(6)
t
PUW(6)
t
R
V
CC
PARAMETER
Power-up to initiation of read operation
Power-up to initiation of write operation
V
CC
Power up ramp rate
0.2
MIN
TYP
MAX
1
5
50
UNIT
ms
ms
V/msec
Power-up Requirements
(Power Up sequencing can affect
correct recall of the wiper registers)
The preferred power-on sequence is as follows: First Vcc,
then the potentiometer pins. It is suggested that Vcc reach
90% of its final value before power is applied to the
potentiometer pins. The Vcc ramp rate specification should
be met, and any glitches or slope changes in the Vcc line
should be held to <100mV if possible. Also, Vcc should not
reverse polarity by more than 0.5V.
Notes:
(5) This parameter is guaranteed by characterization or sample testing.
(6) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
(7) This parameter is guaranteed by design.
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse
width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to
the device.
Symbol Table
AC Conditions of Test
Input pulse levels
Input rise and fall times
Input and output timing levels
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11
FN8164.1
September 15, 2005
INTERSIL [ INTERSIL CORPORATION ]
