X9241A
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1 P0
R1 R0
A
C
K
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
P1 P0 R1 R0
A CM DW D5 D4 D3 D2 D1 D0 A
C
C
K
K
S
T
O
P
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
X
X
P1 P0 R1 R0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
INC/DEC
CMD
ISSUED
SCL
t
CLWV
SDA
Voltage Out
V
W
/R
W
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
6
FN8164.1
September 15, 2005