CMOS, 330 MHz
Triple 10-Bit High Speed Video DAC
PIN FUNCTION DESCRIPTIONS
Pin No.
3-12
Mnemonic
B9-B0
Function
R0, G0, and B0 are the least significant data bits. Unused pixel data
inputs should be connected to either the regular PCB power or ground
plane.
Load detecting result.
When EN_DET=’1’, LDET will output the load detecting result.
2
‘1’: Detecting R
load
> 50 ohm. (Plug-out)
‘0’: Detecting R
load
< 50 ohm. (Plug-in)
Ground.
Digital I/O power supply (1.8V).
Load detecting enable.
‘1’: Enable load detecting circuit to monitor plug-in (out).
‘0’: Disable load detecting circuit.
Data enable.
‘1’: Enable R9-R0, G9-G0 and B9-B0 input to DAC.
‘0’: Disable data input to DAC.
R0, G0, and B0 are the least significant data bits. Unused pixel data
inputs should be connected to either the regular PCB power or ground
plane.
Ground.
Digital I/O power supply (3.3 V).
Clock input (TTL Compatible). The rising edge of CLOCK latches the
R9-R0, G9-G0, and B9-B0 pixel. It is typically the pixel clock rate of the
video system. CLOCK should be driven by a dedicated TTL buffer.
R0, G0, and B0 are the least significant data bits. Unused pixel data
inputs should be connected to either the regular PCB power or ground
plane.
Power-down mode enable.
‘1’: Power-down mode;
When in power-down mode, all functions of this chip are disabled.
Reduced power consumption is available in this mode. There are no
outputs in Pin 53, 54, 56, 57, 59, and 60.
‘0’:Normal mode;
The chip will work correctly in normal mode.
The consuming current of power-down mode and normal mode were
measured in page 2 (power dissipation).
BW0-BW1
Slew rate control inputs.
Slew rate of analog output waveform can be controlled by
BW0-BW1. It is controllable for trade-off between lowering EMI and
output speed.
“00”: slowest slew rate.
……….
“11”: fastest slew rate
1
14
LDET
34-43
R9-R0
市
金
深
圳
合
47,48
讯
科
技
有
限
公
司
46
PWD
，
Te
l:
18
31
32
33
OVSS
OVDD
CLOCK
5
66
43
41
58
21-30
G9-G0
5
QQ
20
DE
:
71
17,44
18,45
19
DVSS
DVDD
EN_DET
44
51
81
9，
廖
R
ITE [ ITE TECH.INC. ]
