LTC2934
APPLICATIONS INFORMATION
VOLꢄAGE (ONIꢄORING
ꢄhreshold Configuration
Unmanaged power can cause various system problems.
Atpower-up,voltagefluctuationaroundcriticalthresholds
can cause improper system or processor initialization.
The LTC2934 provides power management capabilities
for the system power-up phase. The supervisory device
issues a system reset after the monitored voltage has
stabilized. Built-in hysteresis and filtering ensures that
fluctuations due to load transients or supply noise do
not cause chattering of the status outputs. Comparator
undervoltage glitch immunity is shown in the Typical
Performance Characteristics section. The curve dem-
onstrates the transient amplitude and width required to
switch the comparators.
TheLTC2934monitorsvoltageappliedtoitsinputsPFIand
ADJ. A resistive divider connected between a monitored
voltage and ground is used to bias the inputs. Figure 1
demonstrates how the monitor inputs can be made de-
pendent upon a single voltage (V1). Only three resistors
are required. To calculate their values, specify desired
falling power fail (V ) and reset voltages (V ) with V
PF
R
PF
> V . For example:
R
V
PF
= 1.72V, V = 1.62V
R
V1
R3
ADJ
PFI
LTC2934
R2
R1
Because many batteries exhibit large series resistance,
load currents can cause significant voltage drops. The
low DC current draw of the LTC2934 (at any input volt-
age) does not add to the loading problem. When voltage
2934 F01
is initially applied to V , RST and PFO pull low once there
CC
is enough voltage to turn on the pull-down devices (1V
Figure ±1 Configuration for Single Voltage (onitoring
maximum).
The solution for R1, R2, and R3 provides three equations
and three unknowns. Maximum resistor size is governed
by maximum input leakage current. For the LTC2934, the
maximum input leakage current over temperature is 1nA.
For a maximum error of 1% due to both input currents,
the resistor divider current should be 100 times the sum
of the leakage currents, or 0.2μA. At the reset threshold,
If the monitored supply voltage falls to the power-fail
threshold,thebuilt-inpower-failcomparatorpullsPFOlow.
PFO remains low until the PFI input rises above 0.4V plus
2.5%hysteresis.PFOistypicallyusedtosignalpreparation
forcontrolledshutdown.Forexample,thePFOoutputmay
beconnectedtoaprocessornonmaskableinterrupt. Upon
interrupt,theprocessorbeginsshutdownproceduressuch
as supply sequencing and/or storage/erasure of system
state in nonvolatile memory.
V1 = 1.62V, so R
= V1/0.2μA = 8.1M where:
SUM
R
= R1 + R2 + R3
SUM
If the monitored voltage drops below the reset threshold,
RST pulls low until the ADJ input rises above 0.4V plus
5% hysteresis. This may occur through battery charging
or replacement. An internal reset timer delays the return
of the RST output to a high state to provide settling and
initialization time. The RST output is typically connected
to processor reset input.
The falling monitor thresholds (V ) are 0.4 volts, so:
TH
VTH • RSUM
0.4V • 8.1M
1.72V
R1 =
=
= 1.88M
The closest 1% value is 1.87M. R2 can be determined
from:
VTH • RSUM
VR
0.4V • 8.1M
1.62V
Few, if any external components are necessary for reliable
R2 =
– R1 =
− 1.87M
operation. However, a decoupling capacitor between V
and ground is recommended (0.01μF minimum).
CC
R2 = 130k
2934f
7
Linear [ Linear ]
