L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
R
EAD
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L
Symbol Parameter
t
AVAV
t
t
t
t
t
t
t
t
t
PU
0
Output Enable Low to Output Valid
0
6
0
3
7
8
0
6
0
Address Change to Output Change
3
15
3
8
10
0
10
0
Read Cycle Time
15
15
3
20
3
10
10
0
15
0
20
20
3
25
3
15
15
0
20
25
25
3
35
3
20
20
35/35-L 45/45-L
35
35
3
45
45
45
Min Max Min Max Min Max Min Max Min Max
R
EAD
C
YCLE
- A
DDRESS
C
ONTROLLED
Notes 13, 14
t
AVAV
ADDRESS
t
AVQV
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
AVQX
t
PU
I
CC
t
PD
R
EAD
C
YCLE
- CE/OE C
ONTROLLED
N
OTES
13, 15
CE
t
AVAV
t
ELQV
t
ELQX
t
EHQZ
OE
t
GLQX
DATA OUT
HIGH IMPEDANCE
t
GLQV
DATA VALID
t
GHQZ
HIGH
IMPEDANCE
t
PU
Icc
50%
t
PD
50%
LOGIC Devices Incorporated
www.logicdevices.com
4
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC [ LOGIC DEVICES INCORPORATED ]
