L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
R
EAD
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Symbol
t
PD
t
CDR
0
Parameter
Min Max Min Max Min Max Min Max Min Max
15
0
20
0
25
0
35
0
45
D
ATA
R
ETENTION
Notes 9, 10
DATA RETENTION MODE
V
CC
t
CDR
CE
4.5 V
4.5 V
≥2V
t
PD
V
IH
V
IH
W
RITE
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Symbol
t
AVAV
t
ELWH
t
AVWL
t
AVWH
t
WHAX
t
WLWH
t
DVWH
t
WHDX
t
t
Parameter
Write Cycle Time
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Setup to End of Write Cycle
Address Hold After End Of Write
Write Enable Pulse Width Low
Data Setup to End of Write Cycle
Data Hold to End of Write
Min Max Min Max Min Max Min Max Min Max
15
12
0
15
0
12
7
0
5
7
20
12
0
17
0
15
10
0
5
8
25
20
0
20
0
20
12
0
5
10
35
25
0
25
0
30
20
0
5
25
45
35
0
35
0
40
20
0
5
30
LOGIC Devices Incorporated
www.logicdevices.com
5
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC [ LOGIC DEVICES INCORPORATED ]
