LSI/CSI
UL
®
LS7060C
LS7061C
(631) 271-0400 FAX (631) 271-0405
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
32 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
ADVANCE INFORMATION
FEATURES:
• DC to 50MHz Count Frequency
• Byte Multiplexer
• DC to 10MHz Byte Output Scan Frequency
• +4.75V to +5.25V Operation (V
DD
- V
SS
)
• Three-State Data Outputs; Bus, TTL and CMOS Compatible
• Inputs TTL and CMOS Compatible
• Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
Counter Systems
• Low Power Dissipation
• LS7060C (DIP), LS7060C-S (SOIC) - See Figure 1
• LS7061C (DIP), LS7061C-S (SOIC) - See Figure 2
DESCRIPTION:
The LS7060C/LS7061C are CMOS Silicon Gate, 32 bit Up
Counters. The ICs include latches, multiplexer, byte output se-
quencer, eight three-state binary data output drivers and output
cascading logic.
DESCRIPTION OF OPERATION:
32 BIT BINARY UP COUNTER - LS7060C (LS7061C)
The 32 bit static ripple through counter increments on the neg-
ative edge of the input count pulse. Maximum ripple time is 20ns
transition count of 32 ones to 32 zeros.
Guaranteed count frequency is DC to 50MHz.
See Figure 9A (9B) for Block Diagram.
COUNT, ALT COUNT
(LS7060C)
Input count pulses to the 32 bit counter may be applied through
either of these two inputs. The ALT COUNT input circuitry con-
tains a Schmitt trigger network which allows proper counting with
"infinitely" long clock edges. A high applied to either of these two
inputs inhibits counting.
COUNT
(LS7061C)
Input count pulses to the 32 bit counter may be applied through
this input. This input is the most significant bit of the external data
byte.
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 20ns. RESET must be high for a minimum of
10ns before next valid count can be recorded.
TEST COUNT
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
NOTE:
LS7060C and LS7061C can directly replace LS7060 and
LS7061 in all existing applications.
7060C/61C-012102-1
January 2002
PIN ASSIGNMENT - TOP VIEW
18
V
DD
(+V)
17
B4 OUT
16
B5 OUT
15
B6 OUT
COUNT
ALT COUNT
B3 OUT
B2 OUT
B1 OUT
B0 OUT
RESET
1
2
3
4
5
6
7
8
9
LSI
LS7060C
14
B7 OUT
13
TEST COUNT
12
SCAN RESET/LOAD
11
ENABLE
10
SCAN
CASCADE EN OUT
V
SS
(-V)
FIGURE 1
PIN ASSIGNMENT - TOP VIEW
1
2
3
4
5
6
LS7061C
7
8
9
10
18
17
16
15
14
13
FIGURE 2
B7 OUT
B3 IN
TEST COUNT
SCAN RESET/LOAD
ENABLE
SCAN
24
23
22
21
20
19
B4 OUT
B5 OUT
B0 IN
B1 IN
B6 OUT
B2 IN
LSI
V
DD
(+V)
(COUNT) B7 IN
B3 OUT
B6 IN
B2 OUT
B5 IN
B1 OUT
B4 IN
B0 OUT
RESET
CASCADE ENABLE OUT 11
Vss (-V)
12
LATCHES
32 bits of latch are provided for storage of counter data for the
LS7060C. 40 bits of latch are provided for the LS7061C of which
eight are for storage of a high speed external prescaling counter
and the remaining 32 are for the contents of the chip counter
data. All latches are loaded when the LOAD input is brought low
for a minimum of 10ns and kept low until a minimum of 20ns has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when LOAD is brought high for a
minimum of 20ns before next negative edge of count pulse or
RESET.
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