SCAN COUNTER AND DECODER
The scan counter is reset to the least significant byte position
(State 1) when SCAN RESET input is brought low for a mini-
mum of 10ns. The scan counter is enabled for counting as long
as the ENABLE input is held low. The counter advances to the
next significant byte position on each negative transition of the
SCAN pulse. When the scan counter advances to State 5 for
the LS7060C or Stage 6 for the LS7061C it disables the Output
Drivers and stops in that state until SCAN RESET is again
brought low.
SCAN
When the scan counter is enabled, each negative transition of
this input advances the scan counter to its next state. When
SCAN is low the Data Outputs are disabled. When SCAN is
brought high the Data Outputs are enabled and present the
latched counter data corresponding to the present state of the
scan counter. Therefore, in microprocessor applications, the
Data Output Bus may be utilized for other activities while new
data is propagating to the outputs. This positive SCAN pulse
can be viewed as a "Place the next byte on my bus" instruction
from the microprocessor. Minimum positive and negative pulse
widths of 10ns for the SCAN signal are required for scan
counter operation.
SCAN RESET/LOAD
When this input is brought low for a minimum of 10ns, the scan
counter is reset to State 1, the least significant byte position,
and the latches are simultaneously loaded with new count
information.
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
StorageTemperature
Operating Temperature
Voltage (any pin to V
SS
)
ENABLE
When this input is high, the scan counter and the Data Outputs are
disabled. When ENABLE is low, the scan counter and Data Outputs
are enabled for normal operation. Transition of this input should
only be made while the SCAN input is in a low state in order to pre-
vent false clocking of the scan counter.
CASCADE ENABLE
This output is normally high. It transitions low and stays low when
the scan counter advances to State 5 for LS7060C and State 6 for
LS7061C. In a multiple counter system this output is connected to
the ENABLE input of the next counter in the cascade string. The
SCAN input and SCAN RESET/LOAD input are carried to all the
counters in the "Cascade". Counter 1 then presents its bytes of data
to the Output Bus on each positive transition of the SCAN pulse as
previously discussed. When State 5 for LS7060C or State 6 for
LS7061C of Counter 1 is achieved, Counter 2 presents its data to
the Output Bus. This sequence continues until all counters in the
cascade have been addressed. See Figure 5 for an illustration of a
3 device cascade design. This output is TTL and CMOS
compatible.
THREE-STATE DATA OUTPUT DRIVERS
The eight Data Output Drivers are disabled when either ENABLE
input is high, the scan counter is in State 5 for LS7060C and State 6
for LS7061C, or the SCAN input is low. The Output Drivers are TTL
and Bus compatible.
SYMBOL
T
STG
T
A
V
IN
VALUE
-55 to +150
0 to +70
+10 to -0.3
UNIT
°C
°C
V
DC ELECTRICAL CHARACTERISTICS:
(V
DD
= +5V ± 5%, V
SS
= 0V, T
A
= 0˚C to +70˚C unless otherwise noted.)
PARAMETER
Quiescent Power Supply
Current
Power Supply Current
Power Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
CASCADE ENABLE
B0 - B7
Output Low Voltage
CASCADE ENABLE
B0 - B7
Output Source Current
B0 - B7 Outputs
Output Sink Current
B0 - B7 Outputs
Output Leakage Current
B0 - B7 (Off State)
Input Capacitance
Output Capacitance
Input Leakage Current
ENABLE, RESET, SCAN
7060C/61C-012102-2
SYMBOL
I
DD
I
DD
I
DD
V
IH
V
IL
MIN
-
MAX
0.5
-
8
V
DD
+0.6
UNIT
mA
mA
mA
V
V
4
-
+3.5
0
CONDITIONS
V
DD
= Max, Outputs No Load,
Ø Frequency
15 MHz Operating Frequency
V
DD
= Max, Outputs No Load
At Maximum Operating Frequency
V
DD
= Max, Outputs No Load
-
-
V
OH
V
OH
+2.4
+2.4
-
-
V
V
I
O
= -6mA, V
DD
= Min
I
O
= -33mA, V
DD
= Min
V
OL
V
OL
Isource
-
-
-34
-36
-38
25
20
10
-
-
-
-
+0.4
+0.4
-
-
-
-
-
-
10
6
12
10
V
V
mA
mA
mA
mA
mA
mA
nA
pF
pF
nA
I
O
= 3mA, V
DD
= Min
I
O
= 10mA, V
DD
= Min
V
O
= +1.2V, V
DD
= Min
V
O
= +0.8V, V
DD
= Min
V
O
= +0.4V, V
DD
= Min
V
O
= +1.2V, V
DD
= Min
V
O
= +0.8V, V
DD
= Min
V
O
= +0.4V, V
DD
= Min
V
O
= +.4V to +2.4V, V
DD
= Min
T
A
= 25˚C, f = 1MHz
T
A
= 25˚C, f = 1MHz
V
DD
= Max
Isink
I
OL
C
IN
C
OUT
I
LI
LSI [ LSI COMPUTER SYSTEMS ]
