71M6543F/H and 71M6543G/GH Data Sheet
VREF
IADC0
IADC1
IADC2
IADC3
IADC4
IADC5
IADC6
IADC7
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
∆Σ_
AD CONVERTER
MUX
and
PREAMP
VBIAS
VBIAS
V3P3A
GNDA GNDD
VLCD V3P3SYS
FIR
V3P3A
-
+
VREF
VREF
VLCD
Voltage
Boost
V3P3D
VBAT
MUX
MUX CTRL
CROSS
Voltage
Regulator
CK32
RTCLK (32KHz)
MCK
PLL
CK32
32KHz
4.9 MHZ
4.9 MHz
DIV
ADC
XIN
XOUT
Oscillator
32 KHz
CKADC
CKFIR
22
VDD
2.5V to logic
CLOCK GEN
CK_4X
MUX
CKMPU_2x
MUX _SYNC
CKCE
< 4.9MHz
CE
STRT
WPULSE
VARPULSE
RTM
32-bit Compute
Engine
MPU RAM
(5 KB)
MEMORY SHARE
LCD_GEN
VLC2
VLC1
VLC0
LCD DRIVER
TEST
TEST
MODE
CE CONTROL
CEDATA
32 0x000...0x2FF
0x0000...0x13FF
8
PROG
0x000...0x3FF
16
WPULSE
Y
S
U
B
_
E
C
Y
S
U
B
R
E
F
X
EEPROM
INTERFACE
VARPULSE
2
DIGITAL I/O
I
P
S
6
COM0..5
SEG Pins
SEGDIO Pins
CKMPU
< 4.9MHz
M
A
R
O
/
I
PB
RTC
RTCLK
VBAT_RTC
SDCK
RX
TX
OPT_RX/
SEGDIO55
OPT_TX/
SEGDIO51/
WPULSE
/
VPULSE
UART0
MPU
(80515)
SDOUT
SDIN
Non-Volatile
CONFIGURATION
RAM
CONFIGURATION
RAM
(I/O RAM)
0x2000...0x20FF
8
MEMORY
SHARE
0x00000
…
FLASH 128
KB
0X1FFFF
17
EMULATOR
PORT
CON-
FIGURATION
PARAMETERS
TEMP
SENSOR
BAT
TEST
OPTICAL
INTERFACE
DATA
0x0000...0xFFFF
8
PROGRAM
0x0000...0xFFFF
8
CKMPU_2x
VBIAS
MPU_RSTZ
POWER FAULT
DETECTION
WAKE
FAULTZ
VSTAT
RTM
3
E_RXTX
E_TCLK
E_RST(Open Drain)
TEST MUX
TEST MUX
2
RESET
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
ICE_E
9/20/2010
Figure 1: IC Functional Block Diagram
v1.2
© 2008–2011 Teridian Semiconductor Corporation
9
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
