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DG403DJ 参数 Datasheet PDF下载

DG403DJ图片预览
型号: DG403DJ
PDF下载: 下载PDF文件 查看货源
内容描述: 改进的双路,高速模拟开关 [Improved, Dual, High-Speed Analog Switches]
分类和应用: 复用器开关复用器或开关信号电路光电二极管输出元件
文件页数/大小: 8 页 / 94 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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Im p ro ve d , Du a l, Hig h -S p e e d An a lo g S w it c h e s  
__________Ap p lic a t io n s In fo rm a t io n  
_____________________P in De s c rip t io n  
DG401  
Op e ra t io n w it h S u p p ly Vo lt a g e s  
Ot h e r t h a n ±1 5 V  
NAME  
D1, D2 Drain (Analog Signal)  
N.C. Not internally connected  
FUNCTION  
DIP/SO  
LCC  
The DG401/DG403/DG405 s witc he s op e ra te with  
±4.5V to ±20V bipolar supplies or with a +10V to +30V  
single supply. In either case, analog signals ranging  
from V+ to V- can be switched. The Typical Operating  
Characteristics graphs illustrate typical analog-signal  
and supply-voltage on-resistance variations. The usual  
on-resistance temperature coefficient is 0.5%/°C (typ).  
1, 8  
2, 10  
1, 3-9,  
11, 16  
2-7  
9, 16  
12, 20  
13, 19  
S2, S1 Source (Analog Signal)  
IN2, IN1 Digital Logic Inputs  
Positive Supply-Voltage  
10, 15  
11  
14  
V+  
Input—connected to  
substrate  
Lo g ic In p u t s  
These devices operate with a single positive supply or  
with bipolar supplies. They maintain TTL compatibility  
with supplies anywhere in the ±4.5V to ±20V range as  
12  
13  
15  
17  
V
L
Logic Supply-Voltage Input  
Ground  
GND  
long as V = +5V. If V is connected to V+ or another  
L
L
Negative Supply-Voltage  
Input  
supply at voltages other than +5V, the devices will  
operate at CMOS-logic-level inputs.  
14  
18  
V-  
DG403  
DIP/SO  
NAME  
FUNCTION  
Ove rvo lt a g e P ro t e c t io n  
Proper power-supply sequencing is recommended for  
a ll CMOS d e vic e s . Do not e xc e e d the a b s olute  
maximum ratings because stresses beyond the listed  
ratings may cause permanent damage to the devices.  
LCC  
1, 8, 3, 6 2, 10, 4, 8 D1-D4 Drain (Analog Signal)  
1, 3, 6, 9,  
2, 7  
N.C.  
Not internally connected  
11, 16  
Always sequence V+ on first, followed by V , V-, and  
L
20, 12,  
5, 7,  
16, 9, 4, 5  
10, 15  
S1-S4 Source (Analog Signal)  
log ic inp uts . If p owe r-s up p ly s e q ue nc ing is not  
p os s ib le , a d d two s ma ll, e xte rna l s ig na l d iod e s in  
s e rie s with s up p ly p ins for ove rvolta g e p rote c tion  
(Figure 1). Adding diodes reduces the analog-signal  
range to 1V below V+ and 1V below V-, without affect-  
ing low s witc h re s is ta nc e a nd low le a ka g e  
characteristics. Device operation is unchanged, and  
the difference between V+ and V- should not exceed  
+44V.  
13, 19  
IN2, IN1 Digital Logic Inputs  
Positive Supply-Voltage  
11  
14  
V+  
Input—connected to  
substrate  
12  
13  
15  
17  
V
Logic Supply-Voltage Input  
Ground  
L
GND  
Negative Supply-Voltage  
Input  
14  
18  
V-  
DG405  
DIP/SO  
V+  
NAME  
FUNCTION  
LCC  
1, 8, 3, 6 2, 10, 4, 8 D1-D4 Drain (Analog Signal)  
1, 3, 6, 9,  
2, 7  
N.C.  
Not internally connected  
11, 16  
20, 12,  
5, 7,  
S
D
16, 9, 4, 5  
10, 15  
S1-S4 Source (Analog Signal)  
13, 19  
IN2, IN1 Digital Logic Inputs  
Positive Supply-Voltage  
V
g
11  
14  
V+  
Input—connected to  
substrate  
12  
13  
14  
15  
17  
18  
V
Logic Supply-Voltage Input  
Ground  
L
V-  
GND  
V-  
Negative Supply Voltage  
Figure 1. Overvoltage Protection Using External Blocking Diodes  
_______________________________________________________________________________________  
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