Im p ro ve d , Du a l, Hig h -S p e e d An a lo g S w it c h e s
______________________________________________Tim in g Dia g ra m s /Te s t Circ u it s
+5V
+15V
+3V
0V
LOGIC
INPUT
tr < 20ns
R = 1000Ω
C = 35pF
L
DG401
DG403
DG405
L
50%
t < 20ns
f
V
L
V+
V = +10V (for t
)
D
V
ON
S
D
OUT
t
OFF
V = -10V (for t
D
)
OFF
V
OUT
IN
GND
0.9 x V
OUT
SWITCH
OUTPUT
V-
LOGIC
INPUT
0V
t
ON
0.9 x V
OUT
V
OUT
0V
-15V
R
L
REPEAT TEST FOR IN2 AND S2
V
= V
D
(
)
OUT
R + r
LOGIC INPUT WAVEFORM IS INVERTED FOR
DS(ON)
L
FOR LOAD CONDITIONS, SEE Electrical Characteristics.
SWITCHES THAT HAVE THE OPPOSITE LOGIC
SENSE CONTROL.
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 2. Switching Time
+5V
+15V
V+
DG401
DG403
DG405
+3V
0V
LOGIC
INPUT
V
L
50%
V
OUT1
D
S
+10V
+10V
V
S
D
OUT2
R
L1
V
OUT1
0.9 x V
OUT
SWITCH
OUTPUT 1
C
L1
IN
R
L2
0V
0V
C
L2
GND
V-
LOGIC
INPUT
V
0.9 x V
OUT
SWITCH
OUTPUT 2
OUT2
R = 1000Ω
C = 35pF
L
0V
-15V
L
t
t
D
D
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 3. Break-Before-Make Interval
+5V
+15V
DG401
DG403
DG405
∆V
OUT
V
L
V+
R
GEN
S
D
V
V
OUT
OUT
C
L
IN
V
GEN
GND
0V
V-
10nF
ON
OFF
ON
-15V
Q = (∆V ) (C )
OUT
L
Figure 4. Charge Injection
6
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