DS1307 64 x 8, Serial, I
2
C Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
(V
CC
= 4.5V to 5.5V;
T
A
= 0°C to +70°C, T
A
= -40°C to +85°C.)
CONDITIONS
MIN
0
4.7
(Note 4)
4.0
4.7
4.0
4.7
0
(Notes 5, 6)
250
1000
300
4.7
TYP
MAX
100
UNITS
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
CAPACITANCE
(T
A
= +25°C)
PARAMETER
Pin Capacitance (SDA, SCL)
Capacitance Load for Each Bus
Line
SYMBOL
C
I/O
C
B
(Note 7)
CONDITIONS
MIN
TYP
MAX
10
400
UNITS
pF
pF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
All voltages are referenced to ground.
Limits at -40°C are guaranteed by design and are not production tested.
I
CCS
specified with V
CC
= 5.0V and SDA, SCL = 5.0V.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
only has to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
C
B
—total capacitance of one bus line in pF.
3 of 14
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
