CMOS, Quad, Serial-Interface
8-Bit DAC
MAX500
Table 3. Unipolar Code Table
DAC CONTENTS
MSB
1111
LSB
1111
ANALOG
OUTPUT
255
+V
REF
––––
256
129
+V
REF
––––
256
Table 4. Bipolar Code Table
DAC CONTENTS
MSB
LSB
1111
ANALOG
OUTPUT
––––
+V
REF
127
128
1
+V
REF
––––
128
0V
1
-V
REF
––––
128
127
-V
REF
––––
128
(
)
1111
(
(
)
)
1000
0001
(
)
1000
1000
0111
0001
0000
1111
1000
0000
V
REF
128
+V
REF
–––– = +
––––
256
2
(
)
0111
1111
127
+V
REF
––––
256
(
(
)
0000
0001
(
(
)
)
0000
0000
0001
0000
1
(
–––
)
256
1
+V
REF
––––
256
0V
)
0000
0000
Note:
1LSB = (V
REF
) (2
-8
) = +V
REF
1
(
–––
)
256
128
-V
REF
–––– = -V
REF
128
(
)
Note:
1LSB = (V
REF
) (2
-8
) = +V
REF
Careful PC board ground layout techniques should be
used to minimize crosstalk between DAC outputs, the
reference input(s), and the digital inputs. This is partic-
ularly important if the reference is driven from an AC
source. Figure 7 shows suggested PC board layouts for
minimizing crosstalk.
+15V
4
V
REF
A/B
14
V
DD
Unipolar Output
In unipolar operation, the output voltages and the refer-
ence input(s) are the same polarity. The unipolar circuit
configuration is shown in Figure 8 for the MAX500. The
device can be operated from a single supply with a
slight increase in zero error (see
Output Buffer
Amplifiers
section). To avoid parasitic device turn-on,
the voltage at V
REF
must always be positive with
respect to AGND. The unipolar code table is given in
Table 3.
+
V
IN
-
5
+
V
BIAS
-
AGND
2
DAC A
V
OUT
A
MAX500
V
SS
3
-5V (OR GND)
DIGITAL INPUTS NOT SHOWN
DGND
6
Figure 10. AGND Bias Circuit
Bipolar Output
Each DAC output may be configured for bipolar opera-
tion using the circuit in Figure 9. One op amp and two
resistors are required per channel. With R1 = R2:
V
OUT
= V
REF
(2D
A
- 1)
where D
A
is a fractional representation of the digital
word in Register A.
Table 4 shows the digital code versus output voltage
for the circuit in Figure 9.
Offsetting AGND
AGND can be biased above DGND to provide an arbi-
trary nonzero output voltage for a “zero” input code. This
is shown in Figure 10. The output voltage at V
OUT
A is:
V
OUT
A = V
BIAS
+ D
A
V
IN
where D
A
is a fractional representation of the digital
input word. Since AGND is common to all four DACs,
all outputs will be offset by V
BIAS
in the same manner.
Since AGND current is a function of the four DAC
codes, it should be driven by a low-impedance source.
V
BIAS
must be positive.
10
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