+5V, Serial-Input, Voltage-Output, 14-Bit DACs
MAX544/MAX545
amplifier’s input resistance forms a resistive divider with
the DAC output resistance, which results in a gain
error. To contribute less than 1/2LSB of gain error, the
input resistance typically must be greater than:
1
1
6.25k
Ω ÷
=
205M
Ω
2
2
14
The settling time is affected by the buffer input capaci-
tance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be
significantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 10.4 time constants to settle to
within 1/2LSB of the final output voltage. The time con-
stant is equal to the DAC output resistance multiplied
by the total output capacitance. The DAC output
capacitance is typically 10pF. Any additional output
capacitance increases the settling time.
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approxi-
mately the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 10.4 = 96ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π (1MHz) = 159ns, then the effective time con-
stant of the combined system is:
96ns
2
+
159ns
2
=
186ns
) (
)
(
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 10.4
·
186ns = 1.93µs.
Unipolar Configuration
Figure 2a shows the MAX544/MAX545 configured for
unipolar operation with an external op amp. The op amp
is set for unity gain, and Table 1 lists the codes for this
circuit.
Bipolar Configuration
Figure 2b shows the MAX545 configured for bipolar
operation with an external op amp. The op amp is set
for unity gain with an offset of -1/2V
REF
. Table 2 shows
the offset binary codes for this circuit.
Power-Supply Bypassing and
Ground Management
For optimum system performance, use PC boards with
separate analog and digital ground planes. Wire-wrap
boards are not recommended. Connect the two ground
planes together at the low-impedance power-supply
source. Connect DGND and AGND together at the IC.
The best ground connection can be achieved by con-
necting the DAC’s DGND and AGND pins together and
connecting that point to the system analog ground
plane. If the DAC’s DGND is connected to the system
digital ground, digital noise may get through to the
DAC’s analog portion.
Bypass V
DD
with a 0.1µF ceramic capacitor connected
between V
DD
and AGND. Mount it with short leads
close to the device. Ferrite beads can also be used to
further isolate the analog and digital power supplies.
Table 1. Unipolar Code Table
DAC LATCH CONTENTS
MSB
LSB
1111 1111 1111 11(00)
1000 0000 0000 00(00)
0000 0000 0000 01(00)
0000 0000 0000 00(00)
ANALOG OUTPUT, V
OUT
V
REF
·
(16,383 / 16,384)
V
REF
·
(8192 / 16,384) = 1/2V
REF
V
REF
·
(1 / 16,384)
0V
Digital Inputs and Interface Logic
The digital interface for the 14-bit DAC is based on a
3-wire standard that is compatible with SPI, QSPI, and
MICROWIRE interfaces. The three digital inputs (CS,
DIN, and SCLK) load the digital input data serially into
the DAC.
LDAC
(MAX545) updates the DAC output
asynchronously.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that opto-
couplers can interface directly to the MAX544/MAX545
without additional external logic. The digital inputs are
compatible with TTL/CMOS-logic levels.
Table 2. Bipolar Code Table
DAC LATCH CONTENTS
MSB
LSB
1111 1111 1111 11(00)
1000 0000 0000 01(00)
1000 0000 0000 00(00)
0111 1111 1111 11(00)
0000 0000 0000 00(00)
( ) = Sub-bits
ANALOG OUTPUT, V
OUT
+V
REF
·
(8191 / 8192)
+V
REF
·
(1 / 8192)
0V
-V
REF
·
(1 / 8192)
-V
REF
·
(8192 / 8192) = -V
REF
10
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