32C408B
4 Megabit (512K x 8-Bit) SRAM
(2)
FIGURE 4. TIMING WAVEFORM OF READ CYCLE (WE = V )
IH
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
V levels.
OL
4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and from device to device.
5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS = V .
IL
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention is necessary during read and
write cycle.
FIGURE 5. SRAM HEAVY ION CROSS SECTION
05.02.02 Rev 7
All data sheets are subject to change without notice
7
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MAXWELL [ MAXWELL TECHNOLOGIES ]
