48SD1616
256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM
DQMU/DQML Truth Table
COMMAND
SYMBOL
CKE=N-1
H
CKE=N
x
DQMU
DQML
x
Upper byte (DQ8 to DQ15) write enable/out-
put enable
ENBU
L
Lower byte (DQ0 to DQ7) write enable/out-
put enable
ENBL
MASKU
MASKL
H
H
H
x
x
x
x
L
x
Upper byte (DQ8 to DQ15) write inhibit/out-
put disable
H
x
Lower byte (DQ0 to DQ7) write inhibit/out-
put disable
H
Note: H: V L: V x V or V
IL
IH
IL
IH
Write: IDID is Needed
Read: IDOD is Needed
The SDRAM can mask input/output data by means of DQMU/DQML.
DQMU masks the upper byte and DQML masks the lower byte.
During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On
the other hand, when DQMU/DQML is set High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the
previous data is held ( the new data is not written). Desired data can be masked during burst read or burst
write by setting DQMU/DQML. For more details, refer to the DQMU/DQML control section of the SDRAM
operating instructions.
01.07.05 REV 4
All data sheets are subject to change without notice 10
©2005 Maxwell Technologies
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
