256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM
Pin Functions:
48SD1616
CLK (
INPUT PIN
):
CLK is the master clock input to this pin. The other input signals are referred at CLK rising
edge.
CS (
INPUT PIN
):
When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS
AND
WE (
INPUT PINS
):
Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operations section.
A0
TO
A12 (
INPUT PINS
):
Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are pre-
charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1
(BS) is pre charged. For details refer to the command operation section.
BA0/BA1 (
INPUT PINS
):
BA0/BA1 are bank select signals (BS). The memory array of the 48SD1616 is divided
into bank 0, bank 1, bank 2 and bank 3. The 48SD1616 contains 8192-row X 512-column X 16-bit. If BA0
and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and
BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.
CKE (
INPUT PIN
):
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for
power-down mode,
clock suspend mode
and
self refresh mode
1
.
DQMU/DQML (
INPUT PINS
):
DQMU/DQML control input/output buffers
Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low, the
output buffer becomes Low-Z. ( The latency of DQMU/DQML during reading is 2 clock cycles.)
Write operation: If DQMU/DQML is High, the previous data is held ( the new data is not written). If the
DQMU/DQML is Low, the data is written. ( The latency of DQMU/DQML during writing is 0 clock cycles.)
DQ0
TO
DQ15 (DQ
PINS
):
Data is input to and output from these pins ( DQ0 to DQ15).
V
CC AND
V
CC
Q (
POWER SUPPLY PINS
):
3.3V is applied. ( V
CC
is for the internal circuit and V
CC
Q is for the output
buffer.)
V
SS AND
V
SS
Q (
POWER SUPPLY PINS
):
Ground is connected. (V
SS
is for the internal circuit and V
SS
Q is for the
output buffer.)
1. Self refresh should only be used at temperatures below 70
°C.
01.07.05 REV 4
Memory
All data sheets are subject to change without notice
7
©2005 Maxwell Technologies
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
