256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM
T
ABLE
4. DC E
LECTRICAL
C
HARACTERISTICS
48SD1616
S
UBGROUPS
1, 2, 3
M
IN
M
AX
2
U
NITS
mA
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Standby Current in Power Down
( input signal stable)
5
Standby Current in non power down
6
Standby Current in non power down
( Input signal stable)
7
Active standby current in power
down
1,2,4
Active standby current in power down
(input signal stable)
2,5
Active standby power in non power
down
1,2,6
Active standby current in non power
down ( input signal stable)
2,7
Burst Operating Current
1,2,8
CAS Latency = 2
CAS Latency = 3
Refresh Current
3
Self Refresh current
9
Input Leakage Current
Output Leakage Current
Output high voltage
S
YMBOL
I
CC2PS
T
EST
C
ONDITIONS
CKE = V
IL
t
CK
= 0
CKE, CS = V
IH
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
CKE = V
IL
t
CK
= 12 ns
CKE = V
IL
t
CK
= 0
CKE, CS = V
IN
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
t
CK
= min
BL = 4
t
RC
= min
V
IH
>V
CC
- 0.2V
V
IL
< 0.2 V
0<V
IN
<V
CC
0<VOUT<V
CC
I
OH
= -4mA
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
20
9
4
3
30
15
mA
mA
mA
mA
mA
mA
mA
Memory
110
145
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-1
-1.5
2.4
220
3
1
1.5
mA
mA
uA
uA
V
I
CC5
I
CC6
I
LI
I
LO
V
OH
I
OL
= 4 mA
1, 2, 3
0.4
V
Output low voltage
V
OL
1. I
CC1
depends on output load conditions when the device is selected. I
CC1
(max) is specified with the output open.
2. One Bank operation.
3. Input signals are changed once per one clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals are V
IH
or V
IL
fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current. Self refresh should only be used at temperatures below 70
°C.
01.07.05 REV 4
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies
All rights reserved.