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5102ALP-RP-F-H 参数 Datasheet PDF下载

5102ALP-RP-F-H图片预览
型号: 5102ALP-RP-F-H
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 20 KHz的A / D转换器 [16-Bit, 20 KHz A/D Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 14 页 / 250 K
品牌: MAXWELL [ MAXWELL TECHNOLOGIES ]
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16-Bit, 20 KHz A/D Converter
T
ABLE
3. A
NALOG
C
HARACTERISTICS
5102ALP
(T
A
= T
MIN TO
T
MAX
; VA+, VD+ = 5V; VA-, VD- = -5V; V
REF
= 4.5V; F
ULL
-S
CALE
I
NPUT
S
INEWAVE
, 200 H
Z
; CLKIN = 1.6 MH
Z
; f
S
= 20
K
H
Z
;
B
IPOLAR
M
ODE
;
FRN M
ODE
; AIN1
AND
AIN2
TIED TOGETHER
,
EACH CHANNEL TESTED SEPARATELY
; A
NALOG
S
OURCE
I
MPEDANCE
= 50 W
WITH
1000
P
F
TO
AGND
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Power Supply Current
11
Positive Analog
Negative Analog
(SLEEP High) Positive Digital
Negative Digital
Power Consumption
11, 12
(SLEEP High)
(SLEEP Low)
Power Supply Rejection
13
Positive Supplies
Negative Supplies
S
YMBOL
I
A+
I
A-
I
D+
I
D-
P
do
P
ds
PSR
PSR
M
IN
--
--
--
--
--
--
--
--
T
YP
8.5
-7.7
0.5
-0.5
85
45
84
84
M
AX
12
-11
1.5
-1.5
mW
130
--
dB
--
--
U
NIT
mA
1. Minimum resolution for which no missing codes are guaranteed over the specified temperature range.
2. Applies after calibration at any temperature within the specified temperature range.
3. Total drift over specified temperature range after calibration at power-up at 25°C.
4. Guaranteed by characterization (5102A die).
5. Wideband noise aliased into the baseband. Referred to the input.
6. Applied only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.
7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN
mode). In PDT, RBT, and SSC modes, asynchronrous delay between the falling edge of HOLD and the start of conversion may
add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns.
8. The 5102ALPRP requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µ s of fine charge. FRN mode
allows 9 clock cycles for fine charge which provides for the minimum 5.625 µ s with a 1.6 MHz clock; however, in PDT, RBT, or
SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles.
9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition
and conversion times described above.
10.Typical value (measured).
11. All outputs unloaded. All inputs at VD+ or DGND.
12.Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).
13.With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipo-
lar mode to 90 dB.
Memory
T
ABLE
4. 5102ALP S
WITCHING
C
HARACTERISTICS
(T
A
= T
MIN TO
T
MAX
; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; I
NPUTS
: L
OGIC
0 = 0V, L
OGIC
1 = VD+; C
L
= 50
P
F)
P
ARAMETER
CLKIN Period
1, 2
CLKIN Low Time
CLKIN High Time
S
YMBOL
t
clk
t
clkl
t
clkh
M
IN
0.5
200
200
01.17.05 R
EV
3
T
YP
--
--
--
M
AX
10
--
--
U
NIT
µs
ns
ns
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies Inc.
All rights reserved.